The present invention relates generally to integrated circuits, and, more particularly, to structural testing of integrated circuits.
Integrated circuits (ICs) integrate various analog and digital components on a single chip. Such ICs may contain manufacturing defects caused by, for example, dust particle contamination during fabrication, which can cause the IC to function incorrectly. Thus, testing ICs to detect manufacturing defects is essential. Design for test (DFT) is a technique that adds testability features to an IC to identify manufacturing defects. DFT enables an automatic-test-equipment (ATE) to execute various fault tests on the IC. The ATE uses test patterns generated by test pattern generators, such as automatic test pattern generators (ATPG), pseudo-random pattern generators (PRPG), and the like, to detect faults in ICs.
DFT automates the detection of design faults and hence reduces the cost and time required for development and execution of the fault tests. DFT techniques include various fault models, such as transition, path delay, and stuck-at fault models. A transition fault model is used to detect a failure of a logic state transition at a particular circuit element of the IC within a specific time period. A path delay fault model calculates a sum of delays at each element in a path within the IC and detects faults by comparing the sum of delays of the path with a delay of a critical path. The stuck-at fault models, such as stuck-at ‘0’ and stuck-at ‘1’ fault models, are used to detect faulty connections between various elements of the IC that cause circuits to be stuck-at a particular logic state, i.e., logic zero or logic one.
Scan testing is a DFT technique. When subjected to scan testing, the IC operates in two modes—a test mode (also referred to as ‘shift operation’) and a functional mode (also referred to as ‘capture operation’). At the beginning of scan testing, the IC is set in the test mode by dividing it into multiple on-chip logic modules. Each logic module is further segmented into scan chains or paths. Digital logic elements (e.g., flip-flops, latches, and registers) of a logic module are connected together, in series, to form the scan chains or paths and are referred to as ‘scan cells’. The ATE provides a first serial test pattern to the scan cells via scan-in pads. Subsequently, the IC is switched to the functional mode, where the scan cells generate test responses based on the test patterns. The IC is then switched back to the test mode and the test responses of the scan paths are observed in each clock cycle at scan-out pads.
The ATPG uses a gate-level representation of a netlist of the IC to generate the test patterns and hence the test patterns are deterministic. With an increase in the digital components in the IC, the scan cells and faults in the IC increase. As the scan cells increase, to maintain a high scan testing efficiency, more test patterns are required. The ATE stores the test patterns and test responses of the scan chains. However, the ATE has a limited memory and a restricted speed, as well as a fixed number of input/output (IO) pads. Further, as the scan-in pads, scan cells, and scan-out pads function synchronously, shift speeds thereof are limited by the shift speed of the scan-out pads as the shift speed of the scan-out pads is the slowest shift speed among these elements. Thus, the test time increases, thereby increasing manufacturing costs.
One solution to overcome the aforementioned problems of scan testing is the use of an another DFT technique called built-in self-test (BIST). BIST is a self-test mechanism provided in the IC to enable self-checking of logic circuits within the IC. BIST is similar to scan testing, but instead of the ATPG, BIST uses a PRPG, such as a linear feedback shift register (LFSR) for generating pseudo-random test patterns. Since BIST does not require any test patterns to be stored in the ATE for fault testing, BIST may be performed in the field. Further, in-field use of BIST eliminates the need of tester data (test patterns and test responses) storage. BIST uses a multiple input shift register (MISR) to generate a signature of the test responses and therefore uses just single scan-out pad to output the signature. For example, BIST procedures are often integrated in ISO 26262 standard compliant automotive devices where in-field testing of a device features is crucial. However, the pseudo-random test patterns applied used during BIST do not provide sufficient fault coverage in a limited time period to locate “hard to detect” faults. Further, BIST does not provide a method to avoid the corruption of the signature with non-deterministic values (also referred to as ‘unknown values’ or ‘X values’).
Another scan testing technique to overcome the tester memory limitation problem is test compression, where the IC will include compression and decompression circuitry for compressing test data and decompressing test patterns. Test compression conforms to conventional design rules and hence, can be easily implemented in an IC.
For a given logic design, an increase in the number of scan chains can shorten the length of each scan chain, resulting in a reduction of time required to shift each test pattern, which can reduce test pattern scan out time.
Despite the above techniques, since the number of components and transistors on a chip has increased dramatically, and is continuing to increase, it would be advantageous to have an IC that can be tested reasonably quickly, can be tested in the field, and does not require large volumes of test data.